Senior ASIC Design Engineer

Company: Cornelis Networks, Inc.
Location: San Jose
Posted on: April 1, 2026

Job Description:

Cornelis Networks delivers the world’s highest performance scale-out networking solutions for AI and HPC datacenters. Our differentiated architecture seamlessly integrates hardware, software and system level technologies to maximize the efficiency of GPU, CPU and accelerator-based compute clusters at any scale. Our solutions drive breakthroughs in AI & HPC workloads, empowering our customers to push the boundaries of innovation. Backed by top-tier venture capital and strategic investors, we are committed to innovation, performance and scalability - solving the world’s most demanding computational challenges with our next-generation networking solutions. We are a fast-growing, forward-thinking team of architects, engineers, and business professionals with a proven track record of building successful products and companies. As a global organization, our team spans multiple U.S. states and six countries, and we continue to expand with exceptional talent in onsite, hybrid, and fully remote roles. Cornelis Networks is seeking talented Senior ASIC Design Engineers with deep expertise in one or more of the critical areas needed to develop world-class SoCs for deployment in high-performance computing, advanced data analytics, and AI interconnect solutions. Ideal candidates will have relevant experience in the networking domain, with proven expertise in 50G, 100G, and 400G Ethernet protocols—including TCP/IP, RDMA/RoCE, and IPSec—and their application in high-speed data processing and networking environments. Key Responsibilities: Implement RTL designs using Verilog/System Verilog for high-speed data paths and packet processing logic. Collaborate with verification engineers to create block- and system-level test plans to ensure comprehensive design coverage. Define timing constraints for RTL blocks and work with Physical Design engineers to optimize timing closure. Support post-silicon validation, collaborating with hardware, firmware, and software teams to debug and resolve ASIC issues. Contribute to performance optimization and power-aware design strategies for Host Fabric Interface subsystems. Minimum Qualifications: B.S. or M.S. degree in Computer Engineering, Electrical Engineering, or related field. 8 years of post-college experience in digital design with proficiency in Verilog and System Verilog. Experience in RTL design for high-speed data paths or packet processing in ASICs. Deep understanding of Host Ethernet adaptor architectures. Familiarity with timing closure and modern physical design methodologies. Proven ability in system-level debug and root cause analysis of technical issues. Strong verbal and written communication skills. Preferred Qualifications: Knowledge of Ethernet architecture and networking protocols. Prior experience with RTL development for Ethernet host adapters and system debug. Expertise in multiple clock domain designs and asynchronous interfaces. 5 years of experience with scripting languages such as TCL, Python, or Perl. Familiarity with EDA tools like Design Compiler, Spyglass, or PrimeTime. Location: This is a remote position for employees residing within the United States. We offer a competitive compensation package that includes equity, cash, and incentives, along with health and retirement benefits. Our dynamic, flexible work environment provides the opportunity to collaborate with some of the most influential names in the semiconductor industry. At Cornelis Networks your base salary is only one component of your comprehensive total rewards package. Your base pay will be determined by factors such as your skills, qualifications, experience, and location relative to the hiring range for the position. Depending on your role, you may also be eligible for performance-based incentives, including an annual bonus or sales incentives. In addition to your base pay, you’ll have access to a broad range of benefits, including medical, dental, and vision coverage, as well as disability and life insurance, a dependent care flexible spending account, accidental injury insurance, and pet insurance. We also offer generous paid holidays, 401(k) with company match, and Open Time Off (OTO) for regular full-time exempt employees. Other paid time off benefits include sick time, bonding leave, and pregnancy disability leave. Cornelis Networks does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. Cornelis Networks is an equal opportunity employer, and all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity or expression, pregnancy, age, national origin, disability status, genetic information, protected veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.

Keywords: Cornelis Networks, Inc., Madera , Senior ASIC Design Engineer, Engineering , San Jose, California